CY7C132 2Kx8 CMOS Dual Port SRAM 30ns – Datasheet

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The CY7C132 is a high-speed CMOS 2K by 8 dual-port static RAM. Two ports are provided to permit independent access to any location in memory. The CY7C132 can be utilized as either a standalone 8-bit dual-port static RAM or as a MASTER dual-port RAM in conjunction with the CY7C142/CY7C146 SLAVE dual-port device in systems requiring 16-bit or greater word widths. It is the solution to applications requiring shared or buffered data such as cache memory for DSP, bit-slice, or multiprocessor designs.

Each port has independent control pins; chip enable (CE), write enable (R/W), and output-enable (OE). BUSY flags are provided on each port. In addition, an interrupt flag (INT) is provided on each port of the 52-pin PLCC version. BUSY signals that the port is trying to access the same location currently being accessed by the other port. On the PLCC version, INT is an interrupt flag indicating that data has been placed in a unique location (7FF for the left port and 7FE for the right port). An automatic power-down feature is controlled independently on each port by the chip enable (CE) pins.

CY7C132 Pinout

CY7C132 Pin Configuration

Pin NoPin NameDescription
16-23I/O OL – I/O 7L Data Inputs/Outputs Pins
25-321/O 0R-I/O 7R Address Inputs/Outputs
33-42A9R-A0RAddress RESET Pins
6-15A0L-A9L Address Latch Pins
1CE’ L Chip Latch Enable Pin
2R/WL Read Write Latch Pin
3BUSY’ L Busy Latch Pin
5OE’ LOutput Enable Pin
24GNDGround Pin
48VCCPower Supply
43OE’ ROutput Enable Reset Pin
44INT’ RInterrupt Reset Pin
45BUSY’RBusy Reset Pin
46R/WR’Read/Write Pin
47CE’ RChip Enable Reset Pin
18VCCPower Supply Pin

CY7C132 Key Feature

  • True Dual-Ported memory cells which allow simultaneous reads of the same memory location
  • 2K x 8 organization
  • 0.65-micron CMOS for optimum speed/power
  • High-speed access: 15 ns
  • Low operating power: ICC = 90 mA (max.)
  • Fully asynchronous operation
  • Automatic power-down

You can download this datasheet for CY7C132 2Kx8 CMOS Dual Port SRAM 30ns – Datasheet from the link given below: