CD4526 Divide-by-N Counter

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CD4526 is a part of the CD4000 IC series. This device is presettable, cascadable, synchronous down counter with a decoded “0” state output for divide−by−N applications. In single stage applications the “0” output is applied to the Preset Enable input. The Cascade Feedback input allows cascade divide−by−N operation with no additional gates required. The IC offers a wide array of applications such as low power dissipation, high noise immunity, and ESD protection. CD4526 is compact in size and is directly interfaceable with other TTL devices and microcontrollers.

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What is a Divide by N Counter?

A Divide by N counter refers to a generic counter that divides the input clock frequency by a factor of N ie; in the case of a divide by 2 counter (N=2), in case you cascade four flip-flops, then the output of every stage is divided by 2, if you are taking the output from the 4th flip-flop, then its output clock frequency is equal to 16 (2^4). A Divide by N counter, also known as a frequency divider counter, could be constructed using a single D-type flip-flop.

CD4526 Key Features

Supply Voltage Range = 3.0 Vdc to 18 Vdc
Logic Edge−Clocked Design: Incremented on Positive Transition of
- Clock or Negative Transition of Inhibit
Asynchronous Preset Enable
Capable of Driving Two Low−Power TTL Loads or One Low−Power
- Schottky TTL Load Over the Rated Temperature Range
Pb−Free Packages are Available*

CD4526 Pinout

Pin No	Pin Name	Description
1	Q3	Output Pin 3 of N Counter
2	P3	Preset Data Input 3
3	PE	Preset Enable
4	INHIBIT	INHIBIT
5	P0	Preset Data Input 0
6	CLK	Clock Signal Pin
7	Q0	Output Pin 0 of N Counter
8	VSS	Source Supply
9	Q1	Output Pin 1 of N Counter
10	RESET	reset/disable pin
11	P1	Preset Data Input 1
12	“0”-OUT	Overflow OR Zero Output Pin
13	CF	Cascade Frequency
14	P2	Preset Data Input 2
15	Q2	Output Pin 2 of N Counter
16	VDD	Drain supply