CD4028 BCD-to-Decimal Decoder

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CD4028 is a BCD to decimal or binary to octal decoder consisting of 4 inputs and 10 output buffers. A BCD code applied to the 4 inputs, A, B, C, and D, resulting in a high level at the selected 1-of-10 decimal decoded outputs. Similarly, a 3-bit binary code applied to inputs A, B, and C is decoded into octal at outputs 0–7. A high level signal at the D input inhibits octal decoding and causes outputs 0–7 to go LOW. The IC is always available in a 16 – [in hermetically sealed dual in line IC package (DIP), making it easy to interface with TTL, CMOS, and NMOS devices. The IC offers many features such as high noise immunity and low thermal dissipation.

What is BCD to Decimal Decoder?

A BCD to Decimal Decoder is a simple logical circuit that can translate a BCD (binary coded decimal) input into a decimnal (0 – 9) output In any BCD to decimal decoder, the inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of valid BCD input logic ensures that all outputs remain OFF for all invalid binary input conditions. These decoders feature TTL inputs and high – performance NPN output transistors designed for use as indicator/relay drivers or as open – collector logic circuit drivers.

CD4028 Key Features

Wide supply voltage range: 3.0V to 15V
High noise immunity: 0.45 VDD (typ.)
Low power TTL compatibility: fan out of 2 driving 74L or 1 driving 74LS
Low power
Glitch free outputs
“Positive logic” on inputs and outputs

CD4028 Pinout

Pin No	Pin Name	Description
1	Q4	output 4 of decoder
2	Q2	output 2 of decoder
3	Q0	output 0 of decoder
4	Q7	output 7 of decoder
5	Q9	output 9 of decoder
6	Q5	output 5 of decoder
7	Q6	output 6 of decoder
8	VSS	source supply
9	Q8	output 8 of decoder
10	A	address input 0
11	D	address input 1
12	C	address input 2
13	B	address input 3
14	Q1	output 1 of decoder
15	Q3	output 3 of decoder
16	VDD	Drain supply