CD4013 Dual D Flip-Flop with Set Reset

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CD4013 is a part of the CD4000 IC series. CD4013 consists of two D-flip flops, constructed by using the complementary MOS (CMOS) technology, integrated with p-type and n-type enhancement mode transistors. Each flip-flop has independent data, set, reset, and clock inputs and “Q” and “Q” outputs. These devices can be used for shift register applications, and by connecting “Q” output to the data input, for counter and toggle applications. Setting or resetting is independent of the clock and is accomplished by a high level on the set or reset line respectively. The IC has a wide variety of operating voltages, a wide variety of working conditions, and directly interfaces with CMOS, NMOS & TTL devices. CD4013 offers various features such as high noise immunity and low power dissipation.

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What is D Flip-Flop?

A D-type Latch/flip-flop is best described as a clocked latch, that has two stable states. A D-type latch operates with a delay in input by one clock cycle. Thus, by cascading many D-type flip-flops delay circuits can be created, which are used in many applications such as in digital television systems. A D-type flip-flop is also known as a D flip-flop or a delay flip-flop.

CD4013 Key Features

Wide supply voltage range: 3.0V to 15V
High noise immunity: 0.45 VDD (typ.)
Low power TTL: fan out of 2 driving 74L
compatibility: or 1 driving 74LS

CD4013 Pinout

Pin No	Pin Name	Description
1	Q1	output 1 of flip flop 1
2	Q1′	complement output 1 of flip flop 1
3	CLK 1	clock signal 1 of flip flop 1
4	R1	reset value 1 of flip flop 1
5	D1	data signal 1 of flip flop 1
6	SET 1	set value 1 of flip flop 1
7	VSS	source supply
8	SET 2	set value 2 of flip flop 2
9	D2	data signal 2 of flip flop 2
10	R2	reset value 2 of flip flop 2
11	CLK 2	clock signal 2 of flip flop 2
12	Q2	output 2 of flip flop 2
13	Q2′	complement output 2 of flip flop 2
14	VDD	Drain supply