8250A Asynchronous Communication Element as a serial data input/output interface in a microcomputer system. The system software determines the functional configuration of the UART via a TRI-STATE 8-bit bidirectional data bus. The UART performs serial-to-parallel conversion on data characters received from a peripheral device or a MODEM and parallel-to-serial conversion on data characters received from the CPU.
The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operations being performed by the UART, as well as any error conditions (parity, overrun, framing, or break interrupt).
8250 Pinout
8250 Pin Configuration
| Pin Number | Pin Name | Description |
|---|---|---|
| 1-8 | D0-D7 | Data Bits |
| 9 | RCL K | 16x Baud Rate Clock Input |
| 10 | SER IN | Serial Data Input |
| 11 | SER OUT | Serial Data Output |
| 12 | CS0 | Chip Select |
| 13 | CS1 | Chip Select |
| 14 | CS2 | Chip Select (Active Low) |
| 15 | BAUD OUT | 16x Baud Output (Active Low) |
| 16 | XTAL1 | Crystal Input |
| 17 | XTAL2 | Crystal Input |
| 18 | DOSTR | Data Out Strobe (Active Low) |
| 19 | DOSTR | Data Out Strobe |
| 20 | GND | Ground |
| 21 | DISTR | Data In Strobe (Active Low) |
| 22 | DISTR | Data In Strobe |
| 23 | DDIS | Driver Disable |
| 24 | CS OUT | Chip Select Out |
| 25 | ADS | Address Select (Active Low) |
| 26-28 | A2-A0 | Register Select |
| 29 | NC | Not Connected |
| 30 | INT | Interrupt |
| 31 | OUT2 | Output 2 (Active Low) |
| 32 | RTS | Request to Send (Active Low) |
| 33 | DTR | Data Terminal Ready (Active Low) |
| 34 | OUT1 | Output 1 (Active Low) |
| 35 | MR | Master Reset |
| 36 | CTS | Clear to Send (Active Low) |
| 37 | DSR | Data Set Ready (Active Low) |
| 38 | DCD | Data Carrier Detect (Active Low) |
| 39 | RI | Ring Indicator (Active Low) |
| 40 | Vcc | +5V Positive Supply |
8250 Key Features
- Easily interfaces to most popular microprooessors.
- Adds or deletes standard asynchronous communication bits (start, stop an parity) to or from serial data stream.
- Holding and shift registers eliminate the need for precise synchronization between the CPU and the serial data
You can download this datasheet for 8250A Asynchronous Communication Element – Datasheet from the link given below:
