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The 80C51 is a single-chip control-oriented microcontroller that is fabricated on Intel’s reliable CHMOS III-E technology. Being a member of the 8051 controller family, the 80C51 uses the same powerful instruction set, has the same architecture, and is pin-for-pin compatible with the existing MCS 51 controller family of products.
The 80C51 is identical to the 80C51BH. When ordering the 80C51, customers must submit the 64-byte encryption table together with the ROM code. Lock bit 1 will be set to enable the internal ROM code protection and at the same time allows code verification.
80C51 Pinout
80C51 Pin Configuration
| Pin Number | Pin Name | Description |
|---|---|---|
| 1-8 | P1.0-P1.7 | Port 1 |
| 9 | RST | Reset |
| 10 | P3.0/RXD | Port 3.0 / Serial Receive Pin |
| 11 | P3.1/TXD | Port 3.1 / Serial Transmit Pin |
| 12 | P3.2/INT0 | Port 3.2 / Interrupt 0 (Active Low) |
| 13 | P3.3/INT1 | Port 3.3 / Interrupt 1 (Active Low) |
| 14 | P3.4/T0 | Port 3.4 / Timer 0 |
| 15 | P3.5/T1 | Port 3.5 / Timer 1 |
| 16 | P3.6/WR | Port 3.6 / Write (Active Low) |
| 17 | P3.7/RD | Port 3.7 / Read (Active Low) |
| 18 | XTAL2 | Crystal Input |
| 19 | XTAL1 | Crystal Input |
| 20 | Vss | Ground |
| 21-28 | P2.0-P2.7 | Port 2 |
| 29 | PSEN | Program Store Enable (Active Low) |
| 30 | ALE | Address Latch Enable |
| 31 | EA | External Memory Enable (Active Low) |
| 32-39 | P0.7-P0.1 | Port 0 |
| 40 | Vcc | Positive Supply |
80C51 Key Features
- High-Performance CHMOS EPROM
- 24 MHz Operation
- Improved Quick-Pulse Programming Algorithm
- 3-Level Program Memory Lock
- Boolean Processor
- 128-Byte Data RAM
- 32 Programmable I/O Lines
- Two 16-Bit Timer/Counters
- Extended Temperature Range (b40C to a85C)
You can download this datasheet for 80C51 CPU with 128×8 RAM – Datasheet from the link given below:
