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The 80C31 CPU with 128×8 RAM and I/O CHMOS microcontroller products is fabricated on Intel’s reliable CHMOS process and is functionally compatible with the standard 80C31 HMOS microcontroller products. This technology combines the high speed and density characteristics of HMOs with the low power attributes of CHMOS. This combination expands the effectiveness of the powerful MCS 51 microcontroller architecture and instruction set.
80C31 Pinout
80C31 Pin Configuration
| Pin Number | Pin Name | Description |
|---|---|---|
| 1-8 | P1.0-P1.7 | Port 1 |
| 9 | RST | Reset |
| 10 | P3.0/RXD | Port 3.0 / Serial Receive Pin |
| 11 | P3.1/TXD | Port 3.1 / Serial Transmit Pin |
| 12 | P3.2/INT0 | Port 3.2 / Interrupt 0 (Active Low) |
| 13 | P3.3/INT1 | Port 3.3 / Interrupt 1 (Active Low) |
| 14 | P3.4/T0 | Port 3.4 / Timer 0 |
| 15 | P3.5/T1 | Port 3.5 / Timer 1 |
| 16 | P3.6/WR | Port 3.6 / Write (Active Low) |
| 17 | P3.7/RD | Port 3.7 / Read (Active Low) |
| 18 | XTAL2 | Crystal Input |
| 19 | XTAL1 | Crystal Input |
| 20 | Vss | Ground |
| 21-28 | P2.0-P2.7 | Port 2 |
| 29 | PSEN | Program Store Enable (Active Low) |
| 30 | ALE | Address Latch Enable |
| 31 | EA | External Memory Enable (Active Low) |
| 32-39 | P0.7-P0.1 | Port 0 |
| 40 | Vcc | Positive Supply |
80C31 Key Features
- High Performance HMOS Process
- Internal Timers/Event Counters
- 2-Level Interrupt Priorlty Structure
- 32 1/0 Lines (Four 8-Bit Ports)
- 64K External Program Memory Space
- Security Feature Protects EPROM Parts Against Software Piracy
- Boolean Processor
- Bit-Addressable RAM
- Programmable Full Duplex Serial Channel
Application
- Optimizedforcontrolapplications
You can download this datasheet for 80C31 CPU with 128×8 RAM and I/O – Datasheet from the link given below:
