74LS73 Dual JK Negative Edge Triggered Flip-Flop IC – Datasheet

The 74LS73 is a dual in-line JK flip flop IC. It contains two independent negative-edge-triggered J-K flip-flops with individual J-K, clock, and direct clear inputs. The J and K inputs must be stable one setup time prior to the high-to-low clock transition for predictable operation. When the clear is low, it overrides the clock and data inputs forcing the Q output low and the Q\ output high.

What is a J-K Flip Flop?

The JK Flip Flop is basically a gated RS flip flop with the addition of the clock input circuitry. When both the inputs S and R are equal to logic “1”, the invalid condition takes place. Thus to prevent this invalid condition, a clock circuit is introduced. The JK Flip Flop has four possible input combinations because of the addition of the clocked input. The four inputs are “logic 1”, ‘logic 0”. “No change’ and “Toggle”.

74LS73 Pinout

74LS73 Pin Configuration

Pin No	Pin Name	Description
1	CLK1	Clock input pin 1
2	CLR1―	Active low clear pin 1
3	K1	Input pin K1
4	VCC	Supply Voltage
5	CLK2	Clock input pin 2
6	CLR2―	Active low clear pin 2
7	J2	Input pin J2
8	Q2―	Active low output 2 pin
9	Q2	Active high output 2 pin
10	K2	Input pin K2
11	GND	Ground Pin
12	Q1	Active high output 1 pin
13	Q1―	Active low output 1 pin
14	J1	Input pin J1

74LS73 Features & Specifications

• Technology Family: LS
• Dual JK Flip Flop Package IC
• VCC (Min): 4.75V
• VCC (Max): 5.25
• Bits (#): 2
• Operating Voltage (Nom): 5V
• The frequency at a normal voltage (Max): 35MHz
• Propagation delay (Max): 20ns
• IOL (Max): 8mA
• IOH (Max):-0.4mA
• Rating: Catalog
• Available in 14-pin PDIP, GDIP, PDSO packages

Applications

• PCs and notebooks
• Digital Electronics
• Network equipment

You can download this Datasheet for 74LS73A Dual JK Negative Edge Triggered Flip-Flop from the link given below:

See Also: 74LS56 50-to-1 Frequency Divider IC | 74LS14 Schmitt Trigger Hex Inverter IC | 74LS25 Dual 4 – Input NOR Gate IC with Strobe