62256 32Kx8 100ns Low-Power CMOS RAM – Datasheet

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The 62256A is a CMOS static RAM organized 32K-word × 8-bit. It realizes higher performance and low power consumption by employing 0.8 µm Hi-CMOS process technology. The device, packaged in an 8 × 14 mm TSOP with a thickness of 1.2 mm, 450-mil SOP (footprint pitch width), 600-mil plastic DIP, or 300-mil plastic DIP, is available for high-density mounting. TSOP package is suitable for cards, and reverse type TSOP is also provided. It offers low power standby power dissipation; therefore, it is suitable for battery backup systems.

62256 Pinout

62256 Pin Configuration

Pin NoPin NameDescription
1A14 Address Pin 14
2A12 Address Pin 12
3A7Address Pin 7
4A6 Address Pin 6
5A5 Address Pin 5
6A4 Address Pin 4
7A3 Address Pin 3
8A2 Address Pin 2
9A1Address Pin 1
10A0Address Pin 0
11I/O 0Data Inputs/Outputs 0
12I/O 1Data Inputs/Outputs 1
13I/O 2Data Inputs/Outputs 2
14VSSGround Pin
15I/O 3Data Inputs/Outputs 3
16I/O 4Data Inputs/Outputs 4
17I/O 5Data Inputs/Outputs 5
18I/O 6Data Inputs/Outputs 6
19 I/O 7 Data Inputs/Outputs 7
20CS’Chip Select Pin
21A10Address Pin 10
22OE’Output Enable Pin
23A11 Address Pin 11
24A9Address Pin 9
25A8Address Pin 8
26A13Address Pin 13
27WE’Write Enable Pin
28VCCPower Supply Pin

62256 Key Feature

  • High speed: Fast Access time 85/100/120/150 ns (max)
  • Low Power
    • Standby: 5 µW (typ) (L/L-SL version)
    • Operation: 40 mW (typ) (f = 1 MHz)
  • Single 5 V supply
  • Completely static memory
    • No clock or timing strobe required
  • Equal access and cycle times
  • Common data input and output: Three state output
  • Directly TTL compatible: All inputs and outputs
  • Capability of battery back up operation

You can download this datasheet for 62256 32Kx8 100ns Low-Power CMOS RAM – Datasheet from the link given below: