The 514256B is the new generation dynamic RAM organized as 262 144 words by 4-bit. The 514256B utilizes CMOS silicon-gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the 514256B to be packaged in a standard plastic P-DIP-20-2 or plastic P-SOJ-26/20-1. This package size provides high system bit densities and is compatible with commonly used automatic testing and insertion equipment. System-oriented features include a single + 5 V (± 10 %) power supply, direct interfacing with high-performance logic device families such as Schottky TTL.
514256 Pinout
514256 Pin Configuration
| Pin No | Pin Name | Description |
|---|---|---|
| 1 | I/O 1 | Data Input/Output 1 |
| 2 | I/O 2 | Data Input/Output 2 |
| 3 | WRITE’ | Read/Write Input |
| 4 | RAS’ | Row Address Strobe |
| 5 | NC | No Connection |
| 6 | A0 | Address Pin 0 |
| 7 | A1 | Address Pin 1 |
| 8 | A2 | Address Pin 2 |
| 9 | A3 | Address Pin 3 |
| 10 | VCC | Power Voltage |
| 11 | A4 | Address Pin 4 |
| 12 | A5 | Address Pin 5 |
| 13 | A6 | Address Pin 6 |
| 14 | A7 | Address Pin 7 |
| 15 | A8 | Address Pin 8 |
| 16 | OE’ | Output Enable |
| 17 | CAS’ | Column Address Strobe |
| 18 | I/O 3 | Data Input/Output 3 |
| 19 | I/O 4 | Data Input/Output 4 |
| 20 | VSS | Ground Pin |
514256 Key Feature
- Single + 5 V (± 10 %) supply with a built-in VBB generator
- Output unlatched at cycle end allows twodimensional chip selection
- Read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden-refresh and fast page mode capability
- All inputs, outputs and clocks
- TTL-compatible
- 512 refresh cycles/8 ms
- 512 refresh cycles/64 ms
- for L-version only
You can download this datasheet for514256 256k Video RAM – Datasheet from the link given below:
