The 511000 is the new generation dynamic RAN organized 1,048,576 words by 1 bit. The TC511000 utilizes TOSHIBA’s CHAOS Silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and to the system user. Multiplexed address inputs permit the 511000 to be packaged in a standard 18 pin plastic DIP, 26/20 pin plastic SOJ and 20/19 pin plastic ZIP.
The package size provides high system bit densities and is compatible with widely available automated testing and insertion equipment. System-oriented features include a single power supply of 5V±10% tolerance” direct interfacing capability with high-performance logic families such as Schottky TTL. IJTest Mode” function is implemented from Television.
511000 Pinout
511000 Pin Configuration
| Pin No | Pin Name | Description |
|---|---|---|
| 1 | DIN | Data In |
| 2 | WRITE’ | Read/Write Input |
| 3 | RAS’ | Row Address Strobe |
| 4 | TF | Test Function |
| 5 | A0 | Address Pin 0 |
| 6 | A1 | Address Pin 1 |
| 7 | A2 | Address Pin 2 |
| 8 | A3 | Address Pin 3 |
| 9 | VCC | Power Voltage |
| 10 | A4 | Address Pin 4 |
| 11 | A5 | Address Pin 5 |
| 12 | A6 | Address Pin 6 |
| 13 | A7 | Address Pin 7 |
| 14 | A8 | Address Pin 8 |
| 15 | A9 | Address Pin 9 |
| 16 | CAS’ | Column Address Strobe |
| 17 | D OUT | Data Out |
| 18 | VSS | Ground Pin |
511000 Key Feature
- Output unlatched at cycle end allows two-dimensional chip selection
- Common I/O capability using “EARLY WRITE” operation
- Read-Modify-write, CAS before HAS refresh RAS-only refresh, Hidden refresh, Fast Page Mode and Test Mode capability
- All inputs and output TTL compatible
You can download this datasheet for 511000P 1M Video RAM – Datasheet from the link given below:
